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General-purpose CMOS Logic IC Series (BU4S,BU4000B Series)
High Voltage CMOS Logic ICs
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
No.09050EAT04
Description BU4015B series ICs are 4-stage static shift registers, each consisting of 2 circuits. The D flip-flops of each stage share a common reset input, enabling asynchronous reset at any time. BU4021B series ICs are 8-bit static shift registers configured with 8 register cells, each of which has parallel input. Control of the parallel/serial input (P/S) enables serial input/output with clock synchronization and well as parallel input/serial output conversions. BU4094BC series ICs are shift/store registers, each consisting of an 8-bit shift register and an 8-bit latch. Output can be held in the data transfer mode because the data read into the shift register can be latched by the asynchronous strobe input, The BU4538B IC is a monostable multivibrator that can be reset and retriggered from either edge of an input pulse. A wide range of accurate output pulse widths is available because the output pulse width and accuracy are determined by the external timing constants Cx an Rx. The BU4028B IC is a decoder which converts BCD signals into decimal signals. Of the 10 outputs (Q0 ~ Q9), those corresponding to the input codes A-D are set to "H", while the others are set to "L". Features 1) Low power consumption 2) Wide operating supply voltage range 3) High impedance 4) High fan out 5) L-TTL2 and LS-TTL1 inputs can be driven directly. Applications BU4015B: serial / parallel data conversion and ring counter. BU4021B: control circuits, timing circuits and as a general purpose register requiring high degree of noise tolerance. BU4094BC: series/parallel data conversion and data receivers. BU4538B: can obtain the output pulse amplitude with improved accuracy by external capacity and resistance. BU4028B: code conversion, address decoding, memory selection control, demultiplexing or readout and decoding, etc. Lineup High VoltageCMOS Logic
2 4-bit register circuits 1 circuit 2 circuits 1 circuit 1 circuit 8-bit register 8-bit register Monostable multivibrator BCD Decimal
BU4015B/ BU4015BF BU4021B/ BU4021BF BU4094BC/ BU4094BCF/ BU4094BCFV BU4538B
(Dual 4-bit static shift register) (8-bit static shift register) (8-bit bus compatible shift/store register) (Dual high accuracy monostable multivibrator) (BCD to Decimal decoder)
BU4028B
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1/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Absolute Maximum Ratings Parameter Power Supply Voltage Supply Current Operating Temperature Storage Temperature Input Voltage Maximum Junction Temperature Symbol VDD Iin Topr Tstg VIN Tjmax BU4015B BU4021B Limit BU4094BC BU4538B -0.3 to 18 10 -40 to 85 -55 to 150 -0.3 to VDD+0.3 150
Technical Note
BU4028B
Unit V mA V
Recommended Operating Conditions Parameter Operating Power Supply Input Voltage Symbol VDD VIN BU4015B Limit BU4021B BU4094BC BU4538B 3 to 16 (3 to 18V @BU4094BC) 0 to VDD BU4028B Unit V V
Thermal Derating Curve
1400 1200 1000 800 600 400 200 0
85 1250[mV] BU4 620[mV] BU4FV 380[mV] BU4F (*1) (*2) (*3)
Pd [mW]
()Below shows BU4 BU4015B BU4021B BU4094BC BU4538B BU4028B
Power dissipation
(*1) 10.0
25 50 75 100 125 Ta 150 [] 175
(*2) 5.0
(*3) 3.1
Unit mW/
Ambient temperature
When used at Ta=25 or higher the value above is reduced per 1. Power Dissipation is measured by using the sample mounted on a 70mmx70mmx1.6mm FR4 glass-epoxy PCB (cupper area is less than 3%)
Input / Output Equivalent Circuits
VDD
VDD
VDD
VDD
GND
GND
GND
GND
Input
Output
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2/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics(BU4015B) DC Characteristics (Unless otherwise noted VSS=0[V],Ta=25[]) Limits Parameter Symbol Min Typ Max 3.5 Input `H' voltage VIH 7.0 11.0 1.5 Input `L' voltage VIL 3.0 4.0 Input `H' current IIH 0.3 Input `L' current IIL -0.3 4.95 Output `H' voltage VOH 9.95 14.95 0.05 Output `L' voltage VOL 0.05 0.05 -0.16 Output `H' current IOH -0.4 -1.2 0.44 Output `L' current IOL 1.1 3.0 20 Static supply current IDD 40 80
Technical Note
Unit V
V A A V
V
mA
mA
A
VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15
Condition
Fig.No
VIH=15[V] VIL=0[V] IO=0[mA]
1
IO=0[mA] VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VSS or GND
2
1
2
Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] 180 5 Output rising time tTLH 90 ns 10 65 15 100 5 Output falling time TTHL 50 ns 10 40 15 310 5 Propagation delay time tPLH 125 10 ns CLOCK, DQ tPHL 90 15 460 5 Propagation delay time tPLH 180 10 ns RESETQ tPHL 120 15 100 5 Set up time Tsu 50 ns 10 40 15 185 5 Minimum clock pulse 85 10 tW(CLK) ns width 55 15 200 5 Minimum reset pulse 80 10 tW(RST) ns width 60 15 20 5 Maximum clock f (CLK) 6.0 10 MHz frequency Max. 7.5 15 100 5 Maximum clock tr(CLK) 40 10 s rising/falling time tf(CLK) 15 15 Input capacitance CIN 5 pF
Condition
Fig.No
34
56
78
9
10

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3/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics(BU4021B) DC Characteristics (Unless otherwise noted Parameter Input `H' voltage Symbol VIH
Technical Note
Input `L' voltage Input `H' current Input `L' current Output `H' voltage
VIL IIH IIL VOH
Output `L' voltage
VOL
Output `H' current
IOH
Output `L' current
IOL
Static supply current
IDD
VSS=0[V],Ta=25[]) Limits Min Typ Max 3.5 7.0 11.0 1.5 3.0 4.0 0.3 -0.3 4.95 9.95 14.95 0.05 0.05 0.05 -0.16 -0.4 -1.2 0.44 1.1 3.0 20 40 80
Unit V
V A A V
V
mA
mA
A
VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15
Condition
Fig.No
VIH=15[V] VIL=0[V] IO=0[mA]
11
IO=0[mA] VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND
12
11
12
Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] 180 5 Output rising time tTLH 90 ns 10 65 15 100 5 Output falling time tTHL 50 ns 10 40 15 400 5 "L" to "H" 170 10 Propagation delay time tPLH ns CLOCKQ P/SQ 115 15 400 5 "H" to "L" 170 10 Propagation delay time tPHL ns CLOCKQ P/SQ 115 15 150 5 Set up time tsu 50 ns 10 30 15 150 5 Minimum clock pulse tW(CLK) ns 75 10 width 40 15 3.0 5 Maximum clock f (CLK) MHz 6.0 10 frequency Max. 8.0 15 15 5 Maximum clock tr(CLK) s 5.0 10 rising/falling time tf(CLK) 4.0 15 150 5 Minimum P/S tw(P/S) ns 75 10 Control pulse width 40 15 Input capacitance CIN 5 pF
Condition
Fig.No
1315
1416
17
19

20
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4/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics(BU4094BC) DC Characteristics (Unless otherwise noted VSS=0[V],Ta=25[]) Limits Parameter Symbol Min Typ Max 3.5 Input `H' voltage VIH 7.0 11.0 1.5 Input `L' voltage VIL 3.0 4.0 Input `H' current IIH 0.3 Input `L' current IIL -0.3 4.95 Output `H' voltage VOH 9.95 14.95 0.05 Output `L' voltage VOL 0.05 0.05 -0.44 Output `H' current IOH -1.1 -3.0 0.44 Output `L' current IOL 1.1 3.0 5 Static supply current IDD 10 20
Technical Note
Unit V V A A V V mA mA A
VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15
Condition VIH=15[V] VIL=0[V] IO=0[mA] IO=0[mA] VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND
Fig.No 21 22 21 22
Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] 100 200 5 Output rising time tTLH 50 100 ns 10 40 80 15 100 200 5 Output falling time tTHL 50 100 ns 10 40 80 15 350 600 5 Propagation delay time tPLH 125 250 ns 10 CLOCKQS tPHL 95 190 15 230 460 5 Propagation delay time tPLH 110 220 ns 10 CLOCKQ'S tPHL 75 150 15 420 840 5 Propagation delay time tPLH 195 390 10 ns CLOCKQN tPHL 135 270 15 290 580 5 Propagation delay time tPLH 145 290 ns 10 STROBEQN tPHL 100 200 15 140 280 5 3state tPHZ Propagation delay time 75 150 ns 10 tPZH Output EnableQN 55 110 15 140 280 5 3 state tPLZ Propagation delay time 75 150 ns 10 tPZL Output EnableQN 55 110 15 20 125 5 Minimum set up time tsu 8 55 ns 10 DATACLOCK 6 35 15 10 40 5 Minimum hold time tH 10 20 ns 10 CLOCK DATA 5 15 15 100 200 5 Minimum clock pulse tW(CLK) 50 100 ns 10 width 40 80 15 5 Maximum clock tr(CL) NO Limit s 10 rising/falling time tf(CL) 15 1.25 2.5 Maximum clock f CL 2.5 5 MHz frequency 3.0 12.5 100 200 Minimum TwH 40 80 ns strobe pulse width 35 70 Input capacitance CIN 5 pF
Condition RL=1[k] RL=1[k]
Fig.No 23 24 25 26 27 28 29 30 31
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5/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics(BU4538B) DC Characteristics (Unless otherwise noted Parameter Input `H' voltage Symbol VIH
Technical Note
Input `L' voltage Input `H' current Input `L' current Output `H' voltage
VIL IIH IIL VOH
Output `L' voltage
VOL
Output `H' current
IOH
Output `L' current
IOL
Static supply current
IDD
VSS=0[V],Ta=25[]) Limits Min Typ Max 3.5 7.0 11.0 1.5 3.0 4.0 0.3 -0.3 4.95 9.95 14.95 0.05 0.05 0.05 -0.16 -0.4 -1.2 0.44 1.1 3.0 20 40 80
Unit V
V A A V
V
mA
mA
A
VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15
Condition
Fig.No
VIH=15[V] VIL=0[V] IO=0[mA]

IO=0[mA] VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND

Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] Output rising time tTLH Output falling time tTHL Propagation delay time A,BQ,Q Propagation delay time CDQ,Q Minimum input pulse width tPLH tPHL tPLH tPHL tWIN 185 Output pulse width 1 tWOUT1 185 185 8.8 Output pulse width 2 tWOUT2 8.8 8.8 Minimum trigger time Input capacitance trr CIN 100 50 40 100 50 40 300 150 100 250 125 95 50 30 25 200 200 200 9.4 9.4 9.4 0 0 0 5 215 215 215 10.0 10.0 10.0 pF ns ms s ns ns ns ns ns 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15
Condition
Fig.No

3233
3435
36
CX=2000[pF] RX=100[k] CX=0.1[uF] RX=100[k]
38
39

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6/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics(BU4028B) DC Characteristics (Unless otherwise noted Parameter Symbol
Technical Note
Input `H' voltage
VIH
Input `L' voltage Input `H' current Input `L' current Output `H' voltage
VIL IIH IIL VOH
Output `L' voltage
VOL
Output `H' current
IOH
Output `L' current
IOL
Static supply current
IDD
VSS=0[V],Ta=25[]) Limits Min Typ Max 3.5 7.0 11.0 1.5 3.0 4.0 0.3 -0.3 4.95 9.95 14.95 0.05 0.05 0.05 -0.16 -0.4 -1.2 0.44 1.1 3.0 1 2 4
Unit
V
V A A V
V
mA
mA
A
VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15
Condition
Fig.No
VIH=15[V] VIL=0[V] IO=0[mA]
40
IO=0[mA] VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND
41
40
41
Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] 180 5 Output rising time tTLH 90 ns 10 65 15 100 5 Output falling time tTHL 50 ns 10 40 15 300 5 "L" to "H" tPLH ns 130 10 Propagation delay time 90 15 300 5 "H" to "L" tPHL ns 130 10 Propagation delay time 90 15 Input capacitance CIN 5 pF
Condition
Fig.No
42
43
44

45
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7/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics Curves(BU4015B)
50
[BU4015B/F]
Technical Note
600 Propagation Delay Time (CLKQ) [ns]
[BU4015B/F] [BU4015B/F]
50
Output Source Current [mA]
Output Sink Current [mA]
40
VDD=15[V] -40[] 25[] 85[] VDD=10[V] -40[] 25[] 85[] -40[] 25[] 85[] VDD=5[V]
40
VDD=15[V] -40[] 25[] 85[]
500
VDD=3[V]
400 300 200 100 0
Operating Temperature Range
30
30
20
20
-40[] 25[] VDD=10[V] 85[] -40[] 25[] VDD=5[V] 85[]
VDD=5[V] VDD=10[V] VDD=16[V]
10
10
0 0 5 10 Output Voltage [V] 15 20
0 0
5
10 Output Voltage [V]
15
20
-50
-25
0
25
50
75
100
Fig.1 Output source currentvoltage
Propagation Delay Time (RESETQ) [ns] 600 Propagation Delay Time (CLKQ) [ns]
[BU4015B/F]
Fig.2 Output sink currentvoltage
[BU4015B/F]
Fig.3 Propagation delay tPLH CLKQ
Propagation Delay Time (RESETQ) [ns] 800
[BU4015B/F]
Ambient Temperature []
600 500
500 400 300 200
VDD=3[V]
700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 Ambient Temperature []
VDD=10[V] VDD=16[V] Operating Temperature Range VDD=5[V] VDD=3[V]
VDD=3[V]
400 300 200 100 0 -50 -25 0 25 50 75 100 Ambient Temperature []
Operating Temperature Range VDD=5[V]
Operating Temperature Range VDD=5[V]
VDD=10[V]
100
VDD=16[V]
VDD=10[V] VDD=16[V]
0 -50 -25 0 25 50 75 100 Ambient Temperature []
Fig.4 Propagation delay tPHL CLKQ
200
[BU4015B/F]
Fig.5 Propagation delay tPLH RESETQ
100
[BU4015B/F]
Fig.6 Propagation delay tPHL RESETQ
500
[BU4015B/F]
175
Setup Time (QCLK) [ns]
150 125 100 75
VDD=5[V] VDD=3[V]
Minimum Clock Pulse Width [ns]
Operating Temperature Range
Hold Time (CLKQ) [ns]
80
Operating Temperature Range
400
Operating Temperature Range
VDD=3[V]
60
VDD=3[V] VDD=5[V]
300
40
200
VDD=5[V]
50
VDD=10[V]
20
VDD=10[V] VDD=16[V]
100
25
VDD=16[V]
VDD=10[V] VDD=16[V]
0 -50 -25 0 25 50 75 100 Ambient Temperature []
0 -50 -25 0 25 50
0 -50 -25 0 25
75
100
50
75
100
Ambient Temperature []
Ambient Temperature []
Fig.7Set up time tsu QCLK
200
[BU4015B/F]
Fig.8 Hold time th CLKQ Switching characteristics
20[ns] 20[ns]
Fig.9 Minimum CLK pulse width
Minimum Reset Pulse Width [ns]
175 150 125 100 75
Operating Temperature Range
VDD=3[V]
90%
D (Input data)
VDD
50%
10%
VDD=5[V]
tsu
90%
20[ns]
20[ns]
th
GND(VSS) VDD GND(VSS)
50
VDD=10[V]
CLOCK
50% 10%
25
VDD=16[V]
tWH tWL
90%
tPLH
100
tPHL
VOH
0 -50 -25 0 25 50 75 Ambient Temperature []
Q0 () Q0 (Output data)
50% 10%
VOL
Fig.10Minimum RESET pulse width
tTLH
tTHL
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8/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics Curves(BU4021B)
50 Propagation Delay Time (CLKQS) [ns]
[BU4021B/F]
Technical Note
50
[BU4021B/F]
800 700 600 500 400 300 200 100 0
[BU4021B/F]
Output Source Current [mA]
Output Sink Current [mA]
40
VDD=15[V] -40[] 25[] 85[]
40
VDD=15[V] -40[] 25[] 85[]
VDD=3[V]
30
30
Operating Temperature Range VDD=5[V]
20
VDD=10[V] -40[] 25[] 85[]
20
10
-40[] 25[] 85[]
10
-40[] 25[] VDD=10[V] 85[] -40[] 25[] VDD=5[V] 85[]
VDD=10[V]
VDD=16[V]
0 0
VDD=5[V]
0 10 15 20 0 5
5
10 Output Voltage [V]
15
20
-50
-25
0
25
50
75
100
Output Voltage [V]
Ambient Temperature []
Fig.11 Output source currentvoltage
800 Propagation Delay Time (CLKQS) [ns] 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 Ambient Temperature []
VDD=10[V] VDD=16[V] VDD=3[V]
Fig.12 Output sink currentvoltage
800 Propagation Delay Time (P/SQS) [ns] Propagation Delay Time (P/SQS) [ns]
[BU4021B/F]
Fig.13 Propagation delay tPLH CLKQS
800 700 600 500 400 300 200 100 0
VDD=10[V] VDD=16[V] VDD=3[V] [BU4021B/F]
[BU4021B/F]
700 600 500 400
VDD=5[V] VDD=3[V]
Operating Temperature Range VDD=5[V]
Operating Temperature Range
Operating Temperature Range VDD=5[V]
300 200 100 0 -50 -25 0 25 50 75 100 Ambient Temperature []
VDD=10[V] VDD=16[V]
-50
-25
0
25
50
75
100
Ambient Temperature []
Fig.14 Propagation delay tPHL CLKQS
200
Setup Time (DATACLK) [ns]
[BU4021B/F]
Fig.15 Propagation delay tPLH P/SQS
200 180 Hold Time (CLKDATA) [ns] 160 140 120 100 80 60 40 20 0
VDD=5[V] VDD=10[V] VDD=16[V] [BU4021B/F] Operating Temperature Range
Fig.16 Propagation delay tPHL P/SQS
200 180 Minimum CLK Pulse Width [ns] 160 140 120 100 80 60 40 20 0 -50 -25 0
VDD=5[V] Operating Temperature Range [BU4021B/F] VDD=3[V]
175 150 125 100 75 50 25 0 -50
Operating Temperature Range
VDD=3[V]
VDD=3[V]
VDD=5[V] VDD=10[V] VDD=16[V]
VDD=10[V] VDD=16[V]
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
25
50
75
100
Ambient Temperature []
Ambient Temperature []
Ambient Temperature []
Fig.17 Set up time tsu QCLK
200 180 Hold Time (CLKDATA) [ns] 160 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 Ambient Temperature []
VDD=5[V] VDD=10[V] VDD=16[V] [BU4021B/F] Operating Temperature Range VDD=3[V]
Fig.18 Hold time th CLKQ Switching characteristics
20[ns] Parallel Data or Serial Data CLOCK or P/S 90% 50% 20[ns]
Fig.19 Minimum CLK pulse width
VDD
10%
tsu
10%
tW
90% 50%
tr
tf
th
GND(VSS) VDD GND(VSS)
tPLH
OUTPUT 50% 10%
90%
tPHL
VOH
VOL
tTLH
tTHL
Fig.20 Minimum P/S pulse width
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9/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics Curves(BU4094BC)
50
[BU4094BC/F/FV]
Technical Note
50
[BU4094BC/F/FV]
500 Propagation Delay (CLKQs) [ns]
Output Source Current [mA]
VDD=15[V]
30
-40[] 25[] 85[]
Output Sink Current [mA]
40
40
VDD=15[V] -40[] 25[] 85[]
400
30
-40[]
300
tPLH [BU4094BC/F/FV] VDD=3[V] tPHL VDD=5[V] VDD=3[V] VDD=10[V] VDD=5[V] VDD=16[V] VDD=10[V] VDD=16[V]
20
10
VDD=10[V] -40[] 25[] -40[] 85[] 25[] 85[] VDD=5[V]
20
25[] VDD=10[V] 85[] -40[] 25[] VDD=5[V] 85[]
200
10
100
Operating Temperature Range
0 0 5 10 Output Voltage [V] 15 20
0 0 5 10 Output Voltage [V] 15 20
0 -50 -25 0 25 50 75 100 Ambient Temperature []
Fig.21 Output source currentvoltage
500 Propagation Delay Time (CLKQ'S) [ns] Propagation Delay Time (CLKQN) [ns]
[BU4094BC/F/FV] tPHL VDD=3[V] tPLH VDD=5[V] VDD=3[V] VDD=10[V] VDD=5[V] VDD=16[V] VDD=10[V] VDD=16[V]
Fig.22 Output sink currentvoltage
[BU4094BC/F/FV]
Fig.23 Propagation delay CLKQS
Propagation Delay Time (STROBEQN) [ns] 500
[BU4094BC/F/FV] tPLH tPHL VDD=3[V] VDD=3[V] VDD=5[V] VDD=5[V] VDD=10[V] VDD=16[V] VDD=10[V] VDD=16[V]
500
400
400
tPHL
tPLH VDD=3[V] VDD=5[V] VDD=10[V] VDD=16[V]
400
300
300
200
200
VDD=3[V] VDD=5[V] VDD=10[V] VDD=16[V]
300
200
100
Operating Temperature Range
100
Operating Temperature Range
100
Operating Temperature Range
0 -50 -25 0 25 50 75 100 Ambient Temperature []
0 -50 -25 0 25 50 75 100 Ambient Temperature []
0 -50 -25 0 25 50 75 100 Ambient Temperature []
Fig.24 Propagation delay CLKQ'S
Propagation Delay Time (Output EnableQN) [ns]
[BU4094BC/F/FV] tPHL tPLH VDD=3[V] VDD=5[V] VDD=10[V] VDD=16[V]
Fig.25 Propagation delay CLKQN
Propagation Delay Time (Output EnableQN) [ns] 200 50
[BU4094BC/F/FV] tPHL VDD=3[V] VDD=5[V] VDD=3[V] VDD=5[V] tPLH VDD=10[V] VDD=16[V]
Fig.26 Propagation delay STROBEQN
[BU4094BC/F/FV]
200
150
VDD=3[V] VDD=5[V]
150
Setup Time (DATACLK [ns]
40
Operating Temperature Range
30
VDD=3[V]
100
VDD=10[V] VDD=16[V]
100
VDD=10[V] VDD=16[V]
20
VDD=5[V]
50
Operating Temperature Range
50
Operating Temperature Range
10
VDD=10[V] VDD=16[V]
0 -50 -25 0 25 50 75 100 Ambient Temperature []
0 -50 -25 0 25 50 75 100 Ambient Temperature []
0 -50 -25 0
25
50
75
100
Ambient Temperature []
Fig.27 Propagation delay tPHZ Output EnableQN
200
[BU4094BC/F/FV] Operating Temperature Range
Fig.28 Propagation delay tPLZ Output EnableQN
200
Minimum CLK Pulse Width [ns]
[BU4094BC/F/FV] Operating Temperature Range
Fig.29 Set up time tsu DATACLK Switching characteristics are stated on page 14.
Hold Time (CLKDATA) [ns]
150
150
VDD=3[V]
VDD=3[V]
100
VDD=5[V]
100
VDD=5[V] VDD=10[V] VDD=16[V]
50
VDD=10[V] VDD=16[V]
50
0 -50 -25 0 25 50 75 100 Ambient Temperature []
0 -50 -25 0 25 50 75 100 Ambient Temperature []
Fig.30 Hold time tH CLKDATA
Fig.31 Minimum CLK pulse width tW(CLK)
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
10/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Electrical Characteristics Curves(BU4538B)
1000 Propagation Delay Time (AQ) [ns] Propagation Delay Time (CDQ) [ns]
[BU4538B]
Technical Note
1000 Propagation Delay Time (AQ) [ns]
[BU4538B]
800 700 600 500
[BU4538B]
800
Operating Temperature Range VDD=3[V]
800
VDD=3[V]
VDD=3[V]
600
600
Operating Temperature Range VDD=5[V]
Operating Temperature Range
400 300 200 100 0
VDD=5[V]
400
VDD=5[V]
400
200
VDD=10[V] VDD=16[V]
200
VDD=10[V] VDD=16[V]
VDD=10[V] VDD=16[V]
0 -50 -25 0 25
0 100 -50 -25 0 25 50 75 100 Ambient Temperature []
50
75
-50
-25
0
25
50
75
100
Ambient Temperature []
Ambient Temperature []
Fig.32 Propagation delay tPLH AQ
800 Propagation Delay Time (CDQ) [ns]
[BU4538B] Operating Temperature Range
Fig.33 Propagation delay tPHL AQ
200 180 Minimum Input Pulse Width [ns] 160 140 120 100 80 60 40 20 0
VDD=5[V] VDD=3[V] [BU4538B] Operating Temperature Range
Fig.34 Propagation delay tPHL CDQ
200 180 Minimum RESET Pulse Width [ns] 160 140 120 100 80 60 40 20 0 -50 -25 0 25
VDD=10[V] VDD=16[V] VDD=5[V] [BU4538B] Operating Temperature Range
700 600 500 400 300 200 100
VDD=3[V]
VDD=3[V]
VDD=5[V]
VDD=10[V] VDD=16[V]
VDD=10[V] VDD=16[V]
0 -50 -25 0 25 50 75 100 Ambient Temperature []
-50
-25
0
25
50
75
100
50
75
100
Ambient Temperature []
Ambient Temperature []
Fig.35 Propagation delay tPLH CDQ
5
Normalized Pulse Width Change [%] Normalized Pulse Width Change [%]
Fig.36 Minimum input pulse width tWIN
5 4 3 2 1 0 -1 -2 -3 -4 -5 -50 -25
Operating Voltage Range VDD=3[V] VDD=5[V] VDD=16[V] VDD=10[V] [BU4538B]
Fig.37 Minimum RESET pulse width tRESET
4 3 2 1 0 -1 -2 -3 -4 -5 -50 -25 0 25 50
Operating Voltage Range VDD=10[V] VDD=16[V] VDD=3[V] VDD=5[V]
[BU4538B]
75
100
0
25
50
75
100
Fig.38 Output pulse width tWOUT1 (CX=2000[pF],RX=100[k])
Ambient Temperature []
Fig.39 Output pulse width tWOUT2 (CX=0.1[F],RX=100[k])
Ambient Temperature []
Switching Characteristics
A 50% 20[ns] B 50% 20[ns] 90% CD 50% 10% 90% 10%
20[ns] 90% 50% 10% 20[ns]
20[ns]
20[ns] 90% 10%
tPLH
Q
tPLH
tTHL
tTLH
90% 10%
trr
50%
90% 50% 10%
tPHL
50%
WOUT tPLH
Q 50%
tPLH
50%
90% 50% 10%
tPLH
50%
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11/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Reference data(BU4028B)
50
[BU4028B]
Technical Note
50
[BU4028B]
400 350
[BU4028B]
Output Sourace Current [mA]
Output Sink Current [mA]
40
40
-40[]
Output Rise Time [ns]
VDD=15[V]
300 250
VDD=3[V]
30
VDD=15[V] -40[] 25[] 85[]
30
25[] 85[]
VDD=5[V]
200 150 100
VDD=16[V] VDD=10[V]
20
20
-40[] 25[] VDD=10[V] 85[] -40[] 25[] VDD=5[V] 85[]
10
0
VDD=10[V] -40[] 25[] -40[] 85[] 25[] 85[] VDD=5[V]
10
50 0 15 20 -50 -25
Operating Voltage Range
0 15 20 0
0
5
10 Output Voltage [V]
5
10 Output Voltage [V]
0
25
50
75
100
Ambient Temperature []
Fig.40 Output source currentvoltage
400
[BU4028B]
Fig.41 Output sink currentvoltage
500
[BU4028B]
Fig.42 Propagation delay tTLH
500
[BU4028B] VDD=3[V]
350 Output Fall Time [ns] 300 250 200 150 100 50 0 -50 -25 0 25 50
VDD=3[V]
Propagation Delay Time [ns]
400
VDD=3[V]
400 Propagation Delay Time [ns]
300
Operating Temperature Range
300
Operating Temperature Range
Operating Temperature Range VDD=5[V]
200
VDD=5[V] VDD=10[V]
200
VDD=5[V] VDD=10[V] VDD=16[V]
VDD=10[V] VDD=16[V]
100
VDD=16[V]
100
0 75 100 -50 -25 0 25 50 75 100 Ambient Temperature [] Ambient Temperature []
0 -50 -25 0 25 50 75 100 Ambient Temperature []
Fig.43 Propagation delay tTHL
(*) Switching characteristics is shown in P15.
Fig.44 Propagation delay tPLH
Fig.45 Propagation delay tPHL
Description of BU4015B series model FunctionDual 4-bit static shift register 1) Description of operation Dual 4-bit static shift register of BU4015B is configured with 2 independent serial input/parallel output registers of the same 4-state. Each register is provided with an independent clock and reset input having one series data input. Register state is the D type master/slave flip-flop. Data is shifted to the next stage during the rise time of the clock. Each register can be cleared by addition of "H" level to reset. PIN description PIN No. Symbol
Q1 Q2 Q3
PIN arrangement
CLOCK B Q3B Q2B Q1A Q0A RESET A DA VSS
1 16
Block diagram
VDD D8 RESET B Q0B
CLOCK D D CL Q Q D CL Q Q D CL Q Q D CL Q Q Q0
2 CL 3 R D
15
Q3 Q2 Q1 Q0
14
4
13
R
R
R
R
5 Q0 Q1 Q2 Q3 6 CL R D
12
Q1B
RESET
11
Q2B Q3A CLOCK A
7
10
8
9
Truth table
CLOCK D L H X X
XDon't Care
RESET L L L H
Q0 L H L L
Q1 Q0 Q0 L
Q2 Q1 Q1 L
Q3 Q2 Q2 L
No Change
X
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O CLOCKB I Q3B O Q2A O Q1A O Q0A O RESETA I DA I VSS CLOCKA I Q3A O Q2B O Q1B O Q0B O RESETB I DB I VDD
Function Clock input (CHB) Output 3 (CHB) Output 2 (CHA) Output 1 (CHB) Output 0 (CHA) Reset input (CHA) Data input (CHA) Power supply(-) Clock input (CHA) Output 3 (CHA) Output 2 (CHB) Output 1 (CHB) Output 0 (CHB) Reset input (CHB) Data input (CHB) Power supply(+)
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12/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
Technical Note
Description of BU4021B series model Function: 8-stage static shift register 1) Description of operation BU4021B is an 8-bit static shift register capable of parallel input/series output and series input/series output. In parallel operation, DS (data) being asynchronous with the clock is inputted into each F/F and obtained at output. In series operation, DS (data) is triggered by clock. When P/S input level is "H", parallel operation is effective, and when P/S input level is "L", series operation is effective. PIN arrangement Block diagram
PIN description PIN No. Symbol
P5 P6 P7 P8
P8 Q6 Q8 P4 P3 P2 P1 VSS
P1
1 P8 2 Q6 3 Q8 4 P4 5 P3 6 P2 7 P1 8 P/S CLOCK 10 DS 11 Q7 12 Q5 13 P6 14 P7 15 16
P2
P3
P4
VDD P7 P6 P5 Q7 DS
P/S D CLOCK DQ C DQ C DQ C DQ C DQ C DQ CQ DQ CQ D CQ
Q
Q
Q
CLOCK P/S
9
Truth table
CLOCK D L H X X
XDon't Care
RESET L L L H
Q0 L H L
Q1 Q0 Q0 L
Q2 Q1 Q1 L
Q3 Q2 Q2 L
CLOCK
DS X X
P/S H H
Dm L H
Qm* L H
No Change
X
XDon't Care *:Q6,Q7,Q8: outside *Q6,Q7,Q8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P8 Q6 Q8 P4 P3 P2 P1 VSS P/S CLOCK DS Q7 P5 P6 P7 VDD
I/O I O O I I I I I I I O I I I
Function Parallel data input 8 Output 6 Output 8 Parallel data input 4 Parallel data input 3 Parallel data input 2 Parallel data input 1 Power supply(-) Parallel/Serial Clock input Serial data input Output 7 Parallel data input 5 Parallel data input 6 Parallel data input 7 Power supply (+)
Description of BU4094BC series model Function: Dual 4-bit static shift register 1) Description of operation BU4094BC is an 8-stage shift/store register provided in each stage with a data latch with 3-state output. Data read into shift register is read into the latch during the fall time of asynchronous STROBE input, and in the data transfer mode, output can be held. Data is passed through the latch and outputted when the STROBE is in "H" level. Because the parallel output becomes high impedance when the OUTPUT ENABLE terminal is set to "L" level by 3-state, the parallel output can be connected directly with the 8-bit pass line. PIN arrangement PIN description PIN No. Symbol 1 STROBE 2 SERIALIN 3 CLOCK 4 Q1 5 Q2 6 Q3 7 Q4 8 VSS 9 QS 10 Q'S 11 Q8 12 Q7 13 Q6 14 Q5 15 ENABLE 16 VDD
STROBE SERIAL IN CLOCK Q1 Q2 Q3 Q4 VSS
1
STROBE SERIA IN CLOCK OUTPUT ENABLE Q5
16
VDD OUTPUT ENABLE Q5 Q6 Q7 Q8 Q'S QS
2
15
3
14
4
Q1
Q6 Q7
13
5
Q2
12
6
Q3
Q8
11
7
Q4
Q'S
10
8
QS
9
I/O I I I O O O O O O O O O O I
Function Latch input Data input Clock input Parallel data input Q1 Parallel data input Q2 Parallel data input Q3 Parallel data input Q4 Power supply(-) Serial data output QS Serial data output Q'S Parallel data output Q8 Parallel data output Q7 Parallel data output Q6 Parallel data output Q5 Output enable Power supply (+)
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13/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Block diagram
SERIAL IN
Technical Note
Truth table
8 STAGE SHIFT REGISTER
QS Q'S SERIAL OUTPUT
CLOCK
CLOCK
OUTPUT SERIAL STROBE IN ENABLE
Parallel Output
Serial Output
Q1 L H NC Z NC Z
Qn Qn-1 Qn-1 NC Z NC Z
Qs Q7 Q7 Q7 Q7 NC NC
Q's NC NC NC NC Qs Qs
H H H L H
H H L X X H
L H X X X X
STROBE
8 BIT LACTH
OUTPUT ENABLE
3 STATE OUTPUTS
H
Q1
Q8
PARALLEL OUTPUTS
Switching characteristics
WH
CLOCK 50% 50% 50%
tr
90% 10%
tf
DATA
su
STROBE
h
tWL
OUTPUT ENABLE
50%
50%
tPLH
Q1Q7 50% 10% 90%
tPHL
90% 50% 10%
tPLH tPHZ
50% 90%
tPZH tPLZ
10% 10%
tPZL
90%
tTLH
QS
tTHL
tpLH
50%
tPHL
50%
Q'S QS'
tpLH
tpHL
50% 50%
Description of BU4538B series model Function: Dual high accuracy monostable multivibrator 1) Description of operation BU4538B is a re-triggerable monostable multi vibrator. Triggering is possible from either edge of the rise time and fall time of input pulse. Output pulse setting is determined by the time constant (Rx * Cx) of external Rx and Cx. Recommended output pulse amplitude is 200[s]~1[s]. (Cautions on use: In case of system power down, etc., electric charge accumulated in the capacity Cx is discharged to the VDD terminal through protective diode of 2 pins of 14 pins. When the electric current due to accumulated electric charge exceeds 10[mA], IC may be destructed. When a large capacity Cx is used, electric current flowing into the IC can be restricted by inserting the diode Dx.) PIN description PIN No. Symbol I/O Function PIN arrangement Block diagram Passive component 1 T1A T1A connection pin 1(CHA) VDD VDD VDD Passive component T2A T1B 2 T2A DX RX connection pin 2(CHA) CHA CDA T2B 3 CDA I Reset input (CHA) R Q Q CX AA CDB Vref1 Vref2 Output Enable Enable 4 AA I Input A(CHA) Latch Q BA S Q AB 5 BA I Input B(CHA) A Control QA CHB BB 6 QA O Output Q(CHA) B QA 7 QAB O Output QB(CHA) QB Q Q Reset Latch CD S R 8 VSS Power supply(-) 9 QB VSS 9 QBB O Output QB(CHB) 10 QB O Output Q(CHB) Truth table 11 BB I Input B(CHB) 12 AB I Input A(CHB) INPUT OUTPUT 13 CCB I Reset input (CHB) A B CD Q Q Passive component H H 14 T2B connection pin 1(CHB) L L H H H L H H Passive component 15 T1B L H connection pin 2(CHB) X L H L H 16 VDD Power supply (+)
1 16 2 BA 15 3 CD Q Q T1 T2 14 4 13 5 BA 12 6 CD Q Q T1 T2 11 7 10 8
XDon't Care
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14/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
Technical Note
Description of BU4028B series model Function: BCD to decimal decoder 1) Description of operation BU4028B is a decoder to convert BCD signals into decimal signals. Out of 10 outputs of Q0~Q9, output applicable for the input code of A~D becomes "H" level and all other outputs become "L" level. When the input of D is made to be inhibit input by using 3 inputs of A~C, this product can be used as a 1-OF-8 decoder. PIN arrangement
Q4 Q2 Q0 Q7 Q9 Q5 Q6 VSS
1 Q4 16
Block diagram
VDD Q3
A Q2 Q3 Q4 Q0 Q1
2
Q2
Q3
15
3
Q0
Q1
14
Q1 B C D A Q8 IN
C B
4
Q7
B
13
5
Q9
C
12
Q5 Q6 Q7 Q8 Q9
6
Q5
D
11
7
Q6 Q8
A
10
D
8
9
Truth table
INPUT D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H OUTPUT Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 L L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L HL L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L
Switching characteristics
20[ns] 90% 50% 10% tPHL Neg. 90% 50% Output wave Pos. 10% tPLH 20[ns]
Input wave
PIN description PIN Symb No. ol 1 Q4 2 Q2 3 Q0 4 Q7 5 Q9 6 Q5 7 Q6 8 VSS 9 Q8 10 A 11 D 12 C 13 B 14 Q1 15 Q3 16 VDD
I/ O O O O O O O O O I I I I O O
Function Output 4 Output 2 Output 0 Output 7 Output 9 Output 5 Output 6 Power supply(-) Output 8 Input A Input D Input C Input B Output 1 Output 3 Power supply (+)
tTLH
tTHL
Notes for use 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 10. Unused input terminals Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation Insertion of a resistor (100k approx.) is also recommended
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15/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B Ordering part number
Technical Note
B
U
4
0
1
5
4538B 4028B
B
F
V
-
E
2
Part No.
Part No. 4015B 4021B 4094BC
Package None: DIP16 F : SOP16 FV : SSOP-B16
Packaging and forming specification E2: Embossed tape and reel None:Tray,Tube
SOP16

10 0.2 (MAX 10.35 include BURR) 16 9
Tape Quantity Direction of feed
0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.20.3
4.40.2
( reel on the left hand and you pull out the tape on the right hand
)
1
8 0.15 0.1
1.50.1 0.11
1.27
0.4 0.1
0.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
SSOP-B16
5.00.2
16 9

Tape Quantity Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.40.3
4.40.2
0.3Min.
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1
8
0.150.1
1.150.1
0.10
0.1 0.65 0.220.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
.
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16/17
2009.06 - Rev.A
BU4015B,BU4015BF,BU4021B,BU4021BF, BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
Technical Note
DIP16

Container
19.40.3
Tube 1000pcs Direction of products is fixed in a container tube
Quantity
16 9
Direction of feed
6.50.3
1
8
0.51Min.
7.62
3.20.2 4.250.3
0.30.1 2.54 0.50.1 0-15
(Unit : mm)
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.06 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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